As is known, integrated circuits (IC) consist of a plurality of interoperable circuits fabricated on a silicon substrate. The number of interoperable circuits that can be supported by a substrate continues to grow as the art of IC manufacturing advances. Currently, it is not uncommon for an IC to include several million transistors which are configured into tens of thousands of interoperable circuits.
While increasing the number of circuits that can be fabricated on a single IC allows IC users to design smaller and faster products, it presents the IC manufacturer with increased challenges of effectively manufacturing the ICs. One such challenge is how to test newly produced ICs accurately and efficiently.
To facilitate IC testing, most ICs include test circuitry which may account for 17 percent to 30 percent of the circuitry on the IC. Testing is usually done to insure proper logical operations of the circuits and to detect manufacturing defects. To insure proper logical operation, the IC, while in a test mode, is stimulated using known test patterns and monitoring the output response. If the resulting response is as anticipated, it is assumed that the IC is functioning properly. As one can readily appreciate, for VLSI (very large-scale integration) ICs, tens to hundreds of megabytes of test patterns are needed to test most of the IC.
To test for manufacturing defects in CMOS circuits, quiescent current is measured. As is known, a static CMOS circuit conducts only leakage current (quiescent current). If the quiescent current is too high, it indicates that at least one transistor in the circuit has a gate oxide problem or some other leakage problem. In order to detect all possible locations for gate oxide defects, it would be necessary to apply all the combinations of stimuli to toggle every logic gate while measuring the quiescent current. Typically, it takes 100 to 200 milliseconds per measurement; thus, to get close to 100 percent test coverage of a VLSI chip, it would take hundreds of hours. This is unacceptable to an IC manufacturer who requires ICs to be tested in less than ten seconds.
IC manufacturers, thus, have had to compromise between 100 percent testing and testing time. One such compromise solution is to inject a set of scan chains into the IC, stop the stimulus, and measure the quiescent current. To meet the time constraints, the injection of a scan chain can only be stopped about 30 times, which yields a 60 to 80 percent test coverage.
Therefore, a need exists for a method and apparatus that allows for near 100 percent testing coverage of quiescent current in a short period of time.